1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a cell of a flash memory device and a method for fabricating the same.
2. Description of the Related Art
In a flash memory device, even when power supply is interrupted, the information stored in a memory cell is not vanished. Thus, the flash memory device is widely adopted to a memory card used for a computer. A unit cell of a typical flash memory device has a gate structure in which a floating gate and a control gate electrode are sequentially stacked.
FIG. 1 is a cross-sectional view of a unit cell of a conventional flash memory device of the prior art.
Referring to FIG. 1, a source region 3a and a drain region 3b isolated from each other with a channel area being therebetween are formed on a semiconductor substrate 1. A tunnel oxide 5, a floating gate FG', a dielectric film 7 and a control gate electrode CG' are sequentially deposited on the channel area. The semiconductor substrate 1 is a P-type silicon substrate or a P-type well. The source region 3a and the drain region 3b are areas doped with impurity of a conductivity type different from that of the semiconductor substrate 1, i.e., N-type impurity layers. Also, the tunnel oxide 5 is formed of a thin thermal oxide having a thickness of 100 .ANG. or less so that hot carriers generated at the channel area may pass through.
The programming operation of the unit cell shown in FIG. 1 is performed such that a voltage of 5-7 V is applied to the drain region 3b and a voltage of 10-12 V is applied to the control gate electrode CG'. Here, 0 V is applied to the source region 3a and the semiconductor substrate 1. In such a manner, if the respective voltages are applied to the control gate electrode CG', the source region 3a, the drain region 3b and the semiconductor substrate 1 for programming the unit cell, hot carriers, i.e., hot electrons, are generated at the channel area. The hot carriers pass through the tunnel oxide 5 to then be injected into the floating gate FG'. As a result, the programming operation is performed to increase a threshold voltage of the unit cell shown in FIG. 1.
Also, the erasing operation of the information stored in the unit cell shown in FIG. 1 is performed such that the control gate electrode CG' and the semiconductor substrate 1 are grounded, and a high voltage of 12-15 V is applied to the source region 3a. Here, the drain region 3b is floated. In such a manner, if the respective voltages are applied to the control gate electrode CG', the source region 3a, the drain region 3b and the semiconductor substrate 1 for erasing the unit cell, the electrons stored in the floating gate FG' pass through the tunnel oxide 5 by a voltage difference between the floating gate FG' and the source region 3a to then move to the source region 3a. Accordingly, the electrons in the floating gate FG' are all removed. As a result, the erasing operation is performed to adjust the voltage of the unit cell to an initial threshold voltage or below.
FIG. 2 is a schematic equivalent circuit diagram for explaining a capacitive coupling ratio of the unit cell shown in FIG. 1.
Referring to FIG. 2, capacitance C2 caused by the dielectric film 7 exists between the control gate electrode CG' and the floating gate FG', and capacitance C1 caused by the tunnel oxide 5 shown in FIG. 1 exists between the floating gate FG' and the semiconductor substrate 1, i.e., the channel area. Here, if a positive voltage +V.sub.CG and a positive voltage +V.sub.d are applied to the control gate electrode CG' and the drain region 3b, respectively, and 0 V is applied to the source region 3a and the semiconductor substrate 1, for programing the unit cell, the voltage V.sub.FG induced into the floating gate FG' can be expressed in the following formula (1): EQU V.sub.FG.congruent.(C2.div.(C1+C2)).times.V.sub.CG . . . (1)
From the formula (1), it is understood that the voltage induced into the floating gate FG' is close to the voltage applied to the control gate electrode CG' as the capacitance C2 between the control gate electrode CG' and the floating gate FG' increases. Thus, if the capacitance C2 is increased relative to the capacitance C1, the programming efficiency can be increased and the programming voltage applied to the control gate electrode CG' can be reduced.
As a result, in order to increase the programming efficiency of a flash memory cell or reduce the programming voltage, it is necessary to increase the capacitance between a floating gate and a control gate electrode.